The Art of Verification with SystemVerilog Assertions

The Art of Verification with SystemVerilog Assertions (SVA) covers all aspects of SVA with numerous, detailed examples. The book demonstrates how SVA can be harnessed to implement effective, assertion-based verification.

It teaches the SVA language by explaining its usage in the context of practical verification issues. SVA syntax and features are explained in simple and easy-to-understand language. The usage of each construct is illustrated with both simple examples and examples drawn from common verification problems. SVA is used to develop an effective, assertion-based verification strategy for an OCP cache.